A few weeks ago, the big news was that the research alliance of IBM, Global Foundries and Samsung unveiled the world’s first 5 nm chip as we could all read everywhere over the internet [1]. Most notable was however the fact that they reported the use of horizontal gate-all-around field-effect-transistors (GAA-FETs) in which they actually used three nanosheets stacked on top of each other as channel between source and drain. I think that this aspect, and the fact that they showed a very cool transmission-electron-microscopy (TEM) image (see below), probably contributed a lot to the vast amount of attention that the announcement received. These aspects might have been more important than the fact that really a 5 nm technology device was revealed. From the information provided, I even wouldn’t be able to tell if it would qualify as 5 nm as there was no scale-bar in the TEM image and I couldn’t find any other supporting evidence e.g., in terms of performance. Yet, it clearly showed some important progress made in terms of semiconductor scaling. By the way, a year ago, imec already reported similar GAA-FETs with nanowires at the 2016 Symposia on VLSI Technology & Circuits (Honolulu HI, June 13-17, 2016)[2] as you can see in the other TEM image below (now with scale bars). Well, this blog post is not really meant to discuss the devices nor the technology node they belong too. Yet, the GAA-FETs are a nice way to underline the rapidly growing importance of atomic scale processing (ASP) and that is exactly what I want to do here. Read more…